1. Field of the Invention
The invention generally relates to circuits and methods for built-in self tests (BISTs).
2. Description of the Related Art
Intra-system digital data transmission techniques over backplanes and other transmission mediums have migrated from the use of relatively wide data busses with many data lines to the use of high-speed serial links with relatively few data lines. The serial approach can provide the same or greater aggregate bandwidth while simplifying the backplane design by eliminating a great deal of routing congestion and the need for trace length matching. For example, as illustrated in FIG. 1, a common implementation will use a serializer 102 at the transmit end of the link to convert wide bus data 104 into equivalent high-speed serial data 106, and a deserializer 108 at the receive end of the link to convert back to wide bus data 110 for further processing. For full-duplex operation with unidirectional links, both serializer and deserializer operations can be provided at both ends of the backplane, and fully integrated serializer/deserializer (SerDes) devices are widely available from many integrated circuit (IC) vendors.
FIG. 2 illustrates a conventional SerDes transceiver 200. In a normal operational mode, data that is transmitted by the SerDes transceiver 200 is driven onto a transmission line 202 out of a transmitter amplifier (TX) 204. Data that is received by the SerDes transceiver 200 is recovered by a receiver front end (RX) 206. The transmitter data path performs a serializing function through a parallel-in, serial-out (PISO) circuit 208. The parallel-in, serial-out (PISO) circuit 208 is driven by a serial clock provided by the clock synthesis unit (CSU) 210. The receive data path performs a de-serializing function through a serial-in, parallel-out (SIPO) circuit 212. A sampler circuit 214 determines whether the data is a logic zero or a logic one. Both the sampler circuit 214 and the serial-in, parallel-out (SIPO) circuit 212 are driven by a clock recovery unit 216. The clock recovery unit 216 takes as its inputs, both the clock synthesis unit (CSU) serial clock and the incoming data from the receiver front end (RX) 206.
FIG. 3 illustrates a data eye representation of digital data transitions for a serial data waveform observed by the receiver front end (RX) 206. A data eye corresponds to superimposed waveforms for binary bits of “0” and “1” within a bit period. The upper and lower horizontal lines represent the levels of logic ones and zeroes respectively. The diagonal lines represent transitions between logic zeroes and ones. A challenge in recovering data in high-speed waveforms is to place the sampling clock in the center of the data eye. If sampling occurs over a boundary, a logic bit can be misinterpreted, resulting in an error.
The sampler circuit 214 is to strobe the voltage levels of the incoming RX data at a time prescribed by the sampling clock. When the data voltage is higher than a given threshold, the sampler circuit 214 provides a logic one as an output to the serial-in, parallel-out (SIPO) circuit 212. When the data voltage is lower than a given threshold, the sampler circuit 214 provides a logic zero as an output.
FIG. 4 illustrates an example of receive data and a relatively well-aligned sampling clock signal. The RX data is sampled near the center of the data eye and the likelihood of bit errors is relatively low or minimized.
FIG. 5 illustrates an example of receive data and a relatively poorly-aligned sampling clock signal. The frequency of the RX data stream is slightly offset from the frequency of the sampling clock. For data bits D1, D2 and D3, the sampling point is sufficiently close to the center of the data eye that the likelihood of bit errors is relatively small or minimized. However, for data bits D4 and D5, the sampling point is close to the data transition boundary and the likelihood of bit errors is relatively high. At sampling edge S6, the strobe point has moved toward the center of data bit D7 and illustrates an example where the data and the clock are out of synchronization.
In real-world applications, incoming data is typically not well aligned to the serial clock. For example, there can be a static frequency offset between the serial clock and the data frequency. In addition, the data signal can have jitter, which is a time-varying frequency offset. Frequency offsets and jitter occur in varying degrees depending on the nature of the system.
Returning now to FIG. 2, the clock recovery unit 216 tracks the phase of the incoming data edges. The timing of the data edges is compared against the timing of the serial clock supplied by the clock synthesis unit (CSU) 210. If the phase of the data edge leads or lags the phase of the serial clock edge, the clock phase for the sampler circuit 214 is adjusted so that the sampler circuit 214 strobes the incoming RX data well centered to the data eye.
During production test, the full functional path of a SerDes device should be exercised to verify fault-free operation. The transmit data path of the SerDes device is exercised by sending high-speed data traffic out of the transmitter. The receive data path is exercised by receiving high-speed data traffic. One approach to functional testing has been to source and receive data directly from the automated test equipment (ATE) to the device under test (DUT). However, this approach is relatively impractical at relatively-high operating frequencies or data rates.
FIG. 6 illustrates a conventional SerDes device in a loopback configuration for test. A loopback path 602 operatively couples the transmitter amplifier (TX) 204 to the receiver front end (RX) 206. During a test mode, pseudo-random bit stream (PRBS) data is operatively coupled to the transmit path via the transmitter multiplexer (TX MUX) 604. The data is recovered by the receive data path and is provided to the PRBS monitor to check for bit errors. The presence or absence of bit errors (or the frequency of the bit errors) is used to make the pass/fail decision. While illustrated in the context of PRBS, other data patterns can be used, the selection of which will be readily determined by one of ordinary skill in the art based on the requirements of the device under test (DUT).
One drawback to using a loopback test with a conventional SerDes is that the receive data is clocked at the same rate as the transmitter data, i.e., the receive data and the transmit data are frequency locked. Accordingly, the tracking of incoming data with a frequency offset is not a function of the receiver that is exercised with a conventional SerDes and loopback test. Disadvantageously, such frequency offsets can exist in the end-user's application. Fault coverage of the receiver of the SerDes device for the loopback mode can be inadequately tested.
One relatively costly and impractical way to more adequately test a SerDes device is to force a receiver to track a jittered data waveform. See U.S. Pat. No. 5,835,501 to Dalmia, et al., and U.S. Pat. No. 5,793,822 to Anderson, et al., the disclosures of which are incorporated by reference herein in their entirety. Also, see Laquai, Bernd, et al., Testing Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters, IEEE International Test Conference Proceedings (2001 Baltimore, Md.) pgs. 297-304. During production test, the device under test (DUT) is configured to loop jittered data out of the transmitter and into the receiver. If the receiver is unable to track the jittered data, the bit error rate increases, and the device is deemed faulty.
A jittered data signal can be applied by external test equipment such as a bit error rate tester (BERT) for production tests, but this method is costly and does not scale well to relatively high-channel count devices. By following a design for test (DFT) approach, a circuit for jitter generation can be incorporated into the device under test (DUT). Having a jitter generator on board the device is an advantage not only in production test but also in system tests. Advantageously, the jitter generator can be configured for test-mode operation and send jittered data through the system, thereby reducing the need for a BERT.
One approach is to build test features onto the hardware of the automated test equipment (ATE). See Keezer, D. C. et al. “Test Support Processors for Enhanced Testability of High Performance Circuits”, IEEE International Test Conference (1999: Atlantic City, N.J.) pgs. 801-809. One disadvantage to modifying automated test equipment (ATE) is that the hardware is expensively tailored specifically for each device under test. In addition, since the test features are provided in the automated test equipment (ATE) and not in the SerDes device itself, the test features are not available to an end user.
One approach of inducing frequency offsets between the transmitter and receiver is to introduce a phase interpolator into the transmit clock path. See Yee, Ah-lyan, et al., An integratable 1-2.5 Gbps Low Jitter CMOS Transceiver with Built in Self Test Capability, IEEE Symposium on VLSI Circuits (1999: Kyoto, Japan) pgs. 45-46, and U.S. Pat. No. 6,397,042 to Prentice, et al., the disclosure of which is hereby incorporated by reference herein.